Three-dimensional (3D) wafer-to-wafer vertical stack technology seeks to achieve the long-awaited goal of vertically stacking many layers of active IC devices such as processors, programmable devices and memory devices inside a single chip to shorten average wire lengths, thereby reducing interconnect RC delay and increasing system performance. One major challenge of 3D interconnects on a single wafer or in a wafer-to-wafer vertical stack is through-via that provides a signal path for high impedance signals to traverse from one side of the wafer to the other. Through-silicon via (TSV) is typically fabricated to provide the through-via filled with a conducting material that pass completely through the layer to contact and connect with the other TSVs and conductors of the bonded layers.
Currently, TSV process forming a copper via passing through a silicon substrate is combined typical IC process. When the TSV process is right after a contact process, an additional chemical mechanical planarization or polishing (CMP) process is needed to polish the excess Cu overburden to provide surface planarity. Chemical corrosion, photo-corrosion, narrow trench corrosion, and galvanic corrosion are reported to be the possible mechanisms of Cu corrosion during CMP. Galvanic corrosion (also referred to as bimetallic corrosion) occurs due to electrochemical incompatibility between two dissimilar metals that are in electrical and ionic contact. Thus, the additional Cu CMP slurry will cause galvanic corrosion to the contact plug made of tungsten (W), resulting tungsten corrosion.